1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing thereof.
2. Description of Related Art
As the integration scale of semiconductor integrated circuit design has increased, it has become common practice to provide a large-scale integrated circuit (LSI) which contains a high-speed logic circuit and a large-capacity memory on a single semiconductor chip. For achieving higher speed in semiconductor integrated circuit operation, it is desirable to increase the degree of integration by arranging MOS transistors in a finer structure. For higher integration, an increase in wiring density, i.e., a decrease in average wiring length is also preferable.
In particular, a CMOS cell using six transistors has a relatively large margin of operation and a relatively small current for data retention, and therefore is contained in most CMOS SRAMs at present. However, since the memory cell area of the CMOS SRAM cell is rather large, there is a need to reduce the cell area for improvement in device integration.